The present invention relates to field effect transistors, and more specifically, to multi-gate field effect transistors. Multi-gate field effect transistors (FETs) often include a semiconductor fin or similar structure arranged on a substrate. The fin partially defines active regions (source and drain regions) and a channel region of the device. The geometry of the fin provides a multi-gate FET device.
One method for fabricating multi-gate FETs such as FinFETs includes patterning a number of fins on a substrate. Once the fins are patterned, a dummy gate stack that includes a polysilicon material is patterned over portions of the fins. The dummy gate stack may be formed by a material deposition process followed by a patterning and etching process. The dummy gate stack defines the channel regions of the FETs. The active regions may be increased in size and connected to adjacent fins by performing an epitaxial growth process that grows epitaxial semiconductor material from the fins. Once the active regions are formed and doped either during the epitaxial growth process or with an ion implantation process, the dummy gate stack may be removed, and the gate stack may be formed over the channel regions of the fins.
In previous fabrication processes, a number of fins are patterned with substantially equal spacing between the fins. In order to fabricate multi-FET devices that each includes a plurality of fins, one or more fins may be removed from the substrate to isolate each of the multi-FET devices.
FIG. 1 illustrates a perspective view of a prior art example of multi-FET devices in fabrication. In this regard, fins 102 are arranged on a substrate 101. A gate stack 104 that includes a polysilicon material layer 106 and a capping layer 108 has been patterned over the fins 102. The region 110 of the substrate 101 does not include fins 102. The fins 102 that were previously patterned in the region 110 were removed prior to the deposition and patterning of the dummy gate stack 104. The region 110 absent the fins 102, results in a dip or a depression 112 in the surface of the polysilicon layer 106 of the dummy gate stack 104 that is disposed on the region 110 and the capping layer 108 disposed on the polysilicon layer 106 on the region 110.